1. Field of the Invention
The present invention relates to an analog-to-digital converting device and related calibration method and calibration module, and more particularly, to an analog-to-digital converting device capable of eliminating non-ideal effects via adjusting the bit weights of the output digital signal and related calibration method and calibration module.
2. Description of the Prior Art
A successive approximation register (SAR) analog-to-digital converter (ADC) is a type of ADC applying the binary search algorithm in the analog-to-digital conversion process. Generally, the conversion time of the SAR ADC is limited by the external conversion clock. In each clock period of the conversion clock, the SAR ADC samples an analog input and generates bits of a corresponded digital output bit by bit from the most significant bit (MSB) to the least significant bit (LSB).
When the circuit components in the SAR ADC deviates from the original designs as a result of process variations, the resolution of the SAR ADC is downgraded. The non-ideal effects resulting from the process variation can be reduced via increasing the areas of the circuit components. However, the increases in the areas of the circuit components raise the power consumption and increase the chip area of the SAR ADC. Thus, how to reduce the non-ideal effects of the process variation without affecting the circuit performance and the manufacturing cost becomes a topic to be discussed.